View LT3434_5963647.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT3434 1 3434f applicatio s u features typical applicatio u descriptio u high voltage power conversion 14v and 42v automotive systems industrial power systems distributed power systems battery-powered systems wide input range: 3.3v to 60v 3a peak switch current burst mode operation: 100 a quiescent current** low shutdown current: i q < 1 a power good flag with programmable threshold load dump protection to 60v 200khz switching frequency saturating switch design: 0.1 ? peak switch current maintained over full duty cycle range* 1.25v feedback reference voltage easily synchronizable soft-start capability small 16-pin thermally enhanced tssop package high voltage 3a, 200khz step-down switching regulator with 100 a quiescent current the lt ? 3434 is a 200khz monolithic buck switching regulator that accepts input voltages up to 60v. a high efficiency 3a, 0.1 ? switch is included on the die along with all the necessary oscillator, control and logic circuitry. current mode topology is used for fast transient response and good loop stability. innovative design techniques integrated in a new high voltage process achieve high efficiency over a wide input range. efficiency is maintained over a wide output current range by employing burst mode operation at low currents, utilizing the output to bias the internal circuitry, and by using a supply boost capacitor to fully saturate the power switch. patented circuitry maintains peak switch current over the full duty cycle range.* shutdown reduces input supply current to less than 1 a. external synchronization can be implemented by driving the sync pin with logic-level inputs. a single capacitor from the c ss pin to the output provides a controlled output voltage ramp (soft-start). the device also has a power good flag with a programmable threshold and time-out, and thermal shutdown protection. the LT3434 is available in a 16-pin tssop package with exposed pad leadframe for low thermal resistance. 14v to 3.3v step-down converter with 100 a no load quiescent current efficiency and power loss vs load current load current (a) 0.0001 0 efficiency (%) 25 0.001 0.01 0.1 1 3434 ta02b 100 50 75 0.001 power loss (w) 0.01 10 0.1 1 10 v out = 5v v out = 3.3v typical power loss efficiency v in = 12v l = 33 h c out = 100 f supply current vs input voltage input voltage (v) 0 0 supply current ( a) 50 100 10 20 30 40 3434 ta02a 50 150 25 75 125 60 v out = 3.3v v in shdn v c v bias fb pgfb pg LT3434 4.7 f 100v cer 470pf 0.68 f 0.1 f 33 h 4148 1 f sync c t gnd 100 f 6.3v tant v out 3.3v 2a v in 30mq100 4700pf 10k 165k 1% 100k 1% 3434 ta01 27pf sw boost c ss , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. burst mode is a registered trademark of linear technology corporation. *protected by u.s. patents including 6498466. **see burst mode operation section for conditions.
LT3434 2 3434f symbol parameter conditions min typ max units v shdn shdn threshold 1.15 1.3 1.45 v i shdn shdn input current shdn = 12v 520 a minimum input voltage (note 3) 2.4 3 v i vins supply shutdown current shdn = 0v, boost = 0v, fb/pgfb = 0v 0.1 2 a supply sleep current (note 4) bias = 0v, fb = 1.35v 170 250 a fb = 1.35v 45 75 a i vin supply quiescent current bias = 0v, fb = 1.15v 3.2 6 ma bias = 5v, fb = 1.15v 2.6 5 ma minimum bias voltage (note 5) 2.7 3.1 v i biass bias sleep current (note 4) 110 180 a i bias bias quiescent current sync = 3.3v 700 900 a minimum boost voltage (note 6) i sw = 3a 1.8 v input boost current (note 7) i sw = 3a 65 85 ma v ref reference voltage (v ref ) 3.3v < v vin < 60v 1.225 1.25 1.275 v i fb fb input bias current 75 200 na ea voltage gain (note 8) 900 v/v ea voltage g m di(v c )= 10 a 400 650 900 mho ea source current fb = 1.15v 20 40 55 a ea sink current fb = 1.35v 15 30 40 a v c to sw g m 6a/v v c high clamp 2.1 2.2 2.4 v i pk sw current limit 3 4.7 6.5 a (note 1) v in , shdn, bias ..................................................... 60v boost pin above sw ............................................ 35v boost pin voltage ................................................. 68v sync, c ss , pgfb, fb ................................................ 6v operating junctiontemperature range LT3434efe (note 2) ........................ C 40 c to 125 c LT3434ife (note 2) ......................... C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number consult ltc marketing for parts specified with wider operating temperature ranges. LT3434efe LT3434ife absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t j = 25 c. v in = 12v, shdn = 12v, bias = 5v, fb/pgfb = 1.25v, c ss /sync = 0v unless otherwise noted. t jmax = 125 c, ja = 45 c/w, jc(pad) = 10 c/w exposed pad is gnd (pin 17) must be soldered to gnd (pin 8) fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 nc sw v in v in sw boost tcap gnd pgood shdn sync pgfb fb v c bias c ss 17
LT3434 3 3434f electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t j = 25 c. v in = 12v, shdn = 12v, bias = 5v, fb/pgfb = 1.25v, c ss /sync = 0v unless otherwise noted. symbol parameter conditions min typ max units switch on resistance (note 9) 0.1 0.25 ? switching frequency 180 200 230 khz maximum duty cycle 90 92 % minimum sync amplitude 1.5 2.0 v sync frequency range 230 600 khz sync input impedance 45 k ? i css c ss current threshold (note 10) 7 13 20 a i pgfb pgfb input current 25 100 na v pgfb pgfb voltage threshold (note 11) 88 90 92 % i ct c t source current (note 11) 2 3.6 5.5 a c t sink current (note 11) 1 2 ma v ct c t voltage threshold (note 11) 1.16 1.2 1.26 v pg leakage (note 11) 0.1 1 a pg sink current (note 11) pgfb = 1v, pg = 400mv 120 200 a note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LT3434efe is guaranteed to meet performance specifications from 0 c to 125 c junction temperature. specifications over the C40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3434ife is guaranteed and tested over the full C40 c to 125 c operating junction temperature range. note 3: minimum input voltage is defined as the voltage where switching starts. actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. see applications information. note 4: supply input current is the quiescent current drawn by the input pin. its typical value depends on the voltage on the bias pin and operating state of the LT3434. with the bias pin at 0v, all of the quiescent current required to operate the LT3434 will be provided by the v in pin. with the bias voltage above its minimum input voltage, a portion of the total quiescent current will be supplied by the bias pin. supply sleep current is defined as the quiescent current during the sleep portion of burst mode operation. see applications information for determining application supply currents. note 5: minimum bias voltage is the voltage on the bias pin when i bias is sourced into the pin. note 6: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. note 7: boost current is the current flowing into the boost pin with the pin held 3.3v above input voltage. it flows only during switch on time. note 8: gain is measured with a v c swing from 1.15v to 750mv. note 9: switch on resistance is calculated by dividing v in to sw voltage by the forced current (3a). see typical performance characteristics for the graph of switch voltage at other currents. note 10: the c ss threshold is defined as the value of current sourced into the c ss pin which results in an increase in sink current from the v c pin. see the soft-start section in applications information. note 11: the pgfb threshold is defined as the percentage of v ref voltage which causes the current source output of the c t pin to change from sinking (below threshold) to sourcing current (above threshold). when sourcing current, the voltage on the c t pin rises until it is clamped internally. when the clamp is activated, the output of the pg pin will be set to a high impedance state. when the c t clamp is inactive the pg pin will be set active low with a current sink capability of 200 a.
LT3434 4 3434f typical perfor a ce characteristics uw fb voltage oscillator frequency shdn threshold shdn pin current shutdown supply current sleep mode supply current bias sleep current 1.20 voltage (v) 1.21 1.23 1.24 1.25 1.30 1.27 1.22 1.28 1.29 1.26 temperature ( c) C50 0 50 75 3434 g01 C25 25 100 125 temperature ( c) C50 150 frequency (khz) 160 180 190 200 250 220 0 50 75 3434 g02 170 230 240 210 C25 25 100 125 voltage (v) 1.35 3434 g03 1.20 1.10 1.05 1.00 1.40 1.30 1.25 0.15 temperature ( c) C50 0 50 75 C25 25 100 125 shdn voltage (v) 0 0 current ( a) 1.5 2.5 3.5 10 20 30 40 3434 g04 50 4.5 5.5 1.0 2.0 3.0 4.0 5.0 60 t j = 25 c current ( a) 3434 g05 20 10 5 0 25 15 temperature ( c) C50 0 50 75 C25 25 100 125 v in = 60v v in = 42v v in = 12v current ( a) 3434 g06 160 80 40 0 200 120 140 60 20 180 100 v bias = 0v v bias = 5v temperature ( c) C50 0 50 75 C25 25 100 125 current ( a) 3434 g07 160 80 40 0 200 120 140 60 20 180 100 temperature ( c) C50 0 50 75 C25 25 100 125 pgfb threshold voltage (v) 3434 g08 1.16 1.08 1.04 1.00 1.20 1.12 1.14 1.06 1.02 1.18 1.10 temperature ( c) C50 0 50 75 C25 25 100 125 pg sink current current ( a) 3434 g09 200 100 50 0 250 150 temperature ( c) C50 0 50 75 C25 25 100 125
LT3434 5 3434f typical perfor a ce characteristics uw switch peak current limit soft-start threshold vs fb voltage oscillator frequency vs fb voltage temperature ( c) C50 3.0 3.5 4.0 peak switch current (a) 4.5 5.0 5.5 6.0 C25 C0 25 50 3434 g10 75 100 125 fb voltage (v) 0 0 current ( a) 10 20 30 0.2 0.4 0.6 0.8 3434 g11 1.0 40 50 5 15 25 35 45 1.2 soft-start defeated t j = 25 c fb voltage (v) 0 0 frequency (khz) 50 100 150 0.2 0.4 0.6 0.8 3434 g12 1.0 200 250 1.2 t j = 25 c switch on voltage (v cesat ) load current (a) 0.5 0 voltage (mv) 50 150 200 250 500 350 1.5 2.5 3434 g13 100 400 450 300 1.0 2.0 3.0 t j = 125 c t j = 25 c t j = C40 c input voltage (v) 0 0 supply current ( a) 50 100 10 20 30 40 3434 g20 50 150 25 75 125 60 v out = 3.3v supply current vs input voltage load current (a) 0 3.0 input voltage (v) 3.5 4.5 5.0 5.5 2.0 8.0 7.5 3434 g19 4.0 1.0 0.5 2.5 1.5 3.0 6.0 6.5 7.0 start-up v out = 5v v out = 3.3v running start-up running minimum input voltage burst mode threshold vs input voltage minimum on time for continuous mode operation boost current vs load current input voltage (v) 5 0 load current (ma) 100 300 500 10 15 3434 g21 700 900 200 400 600 800 20 burst mode exit (increasing load) burst mode enter (decreasing load) v out = 3.3v l = 33 h c out = 100 f temperature ( c) C50 200 on time (ns) 650 700 550 600 450 400 350 300 250 500 C25 C0 25 50 3434 g22 75 100 125 load current = 0.5a load current = 1a load current = 2a load current (a) 0 0 boost current (ma) 10 30 2.0 70 60 3434 g23 20 1.0 0.5 2.5 1.5 3.0 40 50
LT3434 6 3434f uu u pi fu ctio s nc (pin 1): no connection. sw (pins 2, 5): the sw pin is the emitter of the on-chip power npn switch. this pin is driven up to the input pin voltage during switch on time. inductor current drives the sw pin negative during switch off time. negative voltage is clamped with the external catch diode. maximum nega- tive switch voltage allowed is C0.8v. v in (pins 3, 4): this is the collector of the on-chip power npn switch. v in powers the internal control circuitry when a voltage on the bias pin is not present. high di/dt edges occur on this pin during switch turn on and off. keep the path short from the v in pin through the input bypass capacitor, through the catch diode back to sw. all trace inductance on this path will create a voltage spike at switch off, adding to the v ce voltage across the internal npn. boost (pin 6): the boost pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar npn power switch. without this added voltage, the typical switch voltage loss would be about 1.5v. the additional boost voltage allows the switch to saturate and its voltage loss approximates that of a 0.1 ? fet structure. c t (pin 7): a capacitor on the c t pin determines the amount of delay time between the pgfb pin exceeding its thresh- old (v pgfb ) and the pg pin set to a high impedance state. when the pgfb pin rises above v pgfb , current is sourced from the c t pin into the external capacitor. when the volt- age on the external capacitor reaches an internal clamp (v ct ), the pg pin becomes a high impedance node. the resultant pg delay time is given by t = c ct ? v ct /i ct . if the no load 2a step response step response typical perfor a ce characteristics uw burst mode operation burst mode operation v out 50mv/div i out 500ma/div v in = 12v 5ms/div 3434 g14 v out = 3.3v i q = 100 a v out 50mv/div i out 500ma/div v in = 12v 5 s/div 3434 g15 v out = 3.3v i q = 100 a v out 50mv/div i out 1a/div v in = 12v 500 s/div 3434 g17 v out = 3.3v c out = 100 f v out 50mv/div i out 1a/div v in = 12v 500 s/div 3434 g18 v out = 3.3v c out = 100 f i load(dc) = 500ma
LT3434 7 3434f uu u pi fu ctio s voltage on the pgfb pin drops below v pgfb , c ct will be discharged rapidly to 0v and pg will be active low with a 200 a sink capability. if the c t pin is clamped (power good condition) during normal operation and shdn is taken low, the c t pin will be discharged and a delay period will occur when shdn is returned high. see the power good section in applications information for details. gnd (pins 8, 17): the gnd pin connection acts as the reference for the regulated output, so load regulation will suffer if the ground end of the load is not at the same voltage as the gnd pin of the ic. this condition will occur when load current or other currents flow through metal paths between the gnd pin and the load ground. keep the path between the gnd pin and the load ground short and use a ground plane when possible. the gnd pin also acts as a heat sink and should be soldered (along with the exposed leadframe) to the copper ground plane to reduce thermal resistance (see applications information). c ss (pin 9): a capacitor from the c ss pin to the regulated output voltage determines the output voltage ramp rate during start-up. when the current through the c ss capaci- tor exceeds the c ss threshold (i css ), the voltage ramp of the output is limited. the c ss threshold is proportional to the fb voltage (see typical performance characteristics) and is defeated for fb voltage greater than 0.9v (typical). see soft-start section in applications information for details. bias (pin 10): the bias pin is used to improve efficiency when operating at higher input voltages and light load current. connecting this pin to the regulated output volt- age forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. this architecture increases efficiency espe- cially when the input voltage is much higher than the output. minimum output voltage setting for this mode of operation is 3v. v c (pin 11): the v c pin is the output of the error amplifier and the input of the peak switch current comparator. it is normally used for frequency compensation, but can also serve as a current clamp or control loop override. v c sits at about 0.65v for light loads and 2.2v at maximum load. during the sleep portion of burst mode operation, the v c pin is held at a voltage slightly below the burst threshold for better transient response. driving the v c pin to ground will disable switching and place the ic into sleep mode. fb (pin 12): the feedback pin is used to determine the output voltage using an external voltage divider from the output that generates 1.25v at the fb pin . when the fb pin drops below 0.9v, switching frequency is reduced, the sync function is disabled and output ramp rate control is enabled via the c ss pin. see the feedback section in applications information for details. pgfb (pin 13): the pgfb pin is the positive input to a comparator whose negative input is set at v pgfb . when pgfb is taken above v pgfb , current (i css ) is sourced into the c t pin starting the pg delay period. when the voltage on the pgfb pin drops below v pgfb , the c t pin is rapidly discharged resetting the pg delay period. the pgfb volt- age is typically generated by a resistive divider from the regulated output or input supply. see power good section in applications information for details. sync (pin 14): the sync pin is used to synchronize the internal oscillator to an external signal. it is directly logic compatible and can be driven with any signal between 30% and 70% duty cycle. the synchronizing range is equal to maximum initial operating frequency up to 700khz. when the voltage on the fb pin is below 0.9v the sync function is disabled. see the synchronizing section in applications information for details. shdn (pin 15): the shdn pin is used to turn off the regulator and to reduce input current to less than 1 a. the shdn pin requires a voltage above 1.2v with a typical source current of 3 a to take the ic out of the shutdown state. pg (pin 16): the pg pin is functional only when the shdn pin is above its threshold, and is active low when the internal clamp on the c t pin is below its clamp level and high impedance when the clamp is active. the pg pin has a typical sink capability of 200 a. see the power good section in applications information for details.
LT3434 8 3434f block diagra w 12 fb v c 15 internal ref undervoltage lockout thermal shutdown soft-start foldback detect slope comp antislope comp 1.2v c t clamp 2.4v C + 1.3v 1.25v shdn 9 c ss 14 sync 10 bias 4 v in shdn comp C + C + error amp 11 13 pgfb c t 1.12v C + pg comp 7 burst mode detect 200khz oscillator switch latch current comp driver circuitry r q sw sw s 2 boost 6 pg 16 gnd 17 pgnd 3434 bd 8 v c clamp 3 v in 5 the LT3434 is a constant frequency, current mode buck converter. this means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. in addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. a switch cycle starts with an oscilla- tor pulse which sets the rs latch to turn the switch on. when switch current reaches a level set by the current compara- tor the latch is reset and the switch turns off. output volt- age control is obtained by using the output of the error amplifier to set the switch current trip point. this technique means that the error amplifier commands current to be delivered to the output rather than voltage. a voltage fed system will have low phase shift up to the resonant fre- quency of the inductor and output capacitor, then an abrupt 180 shift will occur. the current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the lc resonant fre- quency. this makes it much easier to frequency compen- sate the feedback loop and also gives much quicker tran- sient response. most of the circuitry of the LT3434 operates from an internal 2.4v bias line. the bias regulator normally draws figure 1. LT3434 block diagram
LT3434 9 3434f block diagra w power from the v in pin, but if the bias pin is connected to an external voltage higher than 3v bias power will be drawn from the external source (typically the regulated output voltage). this improves efficiency. high switch efficiency is attained by using the boost pin to provide a voltage to the switch driver which is higher than the input voltage, allowing switch to be saturated. this boosted voltage is generated with an external capaci- tor and diode. to further optimize efficiency, the LT3434 automatically switches to burst mode operation in light load situations. in burst mode operation, all circuitry associated with controlling the output switch is shut down reducing the input supply current to 45 a. the LT3434 contains a power good flag with a program- mable threshold and delay time. a logic-level low on the shdn pin disables the ic and reduces input suppy current to less than 1 a. applicatio s i for atio wu uu feedback pin functions the feedback (fb) pin on the LT3434 is used to set output voltage and provide several overload protection features. the first part of this section deals with selecting resistors to set output voltage and the remaining part talks about frequency foldback and soft-start features. please read both parts before committing to a final design. referring to figure 2, the output voltage is determined by a voltage divider from v out to ground which generates 1.25v at the fb pin. since the output divider is a load on the output care must be taken when choosing the resistor divider values. for light load applications the resistor values should be as large as possible to achieve peak efficiency in burst mode operation. extremely large values for resistor r1 will cause an output voltage error due to the 50na fb pin input current. the suggested value for the output divider resistor (see figure 2) from fb to ground (r2) is 100k or less. a formula for r1 is shown below. a table of standard 1% values is shown in table 1 for common output voltages. rr v rna out 12 125 125 2 50 = + ? C. .? more than just voltage feedback the fb pin is used for more than just output voltage sensing. it also reduces switching frequency and con- trols the soft-start voltage ramp rate when output voltage is below the regulated level (see the frequency foldback table 1 output r1 output voltage r2 nearest (1%) error (v) (k ? , 1%) (k ? )(%) 2.5 100 100 0 3 100 140 0 3.3 100 165 0.38 5 100 300 0 6 100 383 0.63 8 100 536 C 0.63 10 100 698 C 0.25 12 100 866 0.63 soft-start foldback detect 200khz oscillator C + error amp 1.25v v c 11 fb 12 c ss v out 9 sw LT3434 c1 r1 r2 3434 f02 2 figure 2. feedback network
LT3434 10 3434f applicatio s i for atio wu uu and soft-start current graphs in typical performance characteristics). frequency foldback is done to control power dissipation in both the ic and in the external diode and inductor during short-circuit conditions. a shorted output requires the switching regulator to operate at very low duty cycles. as a result the average current through the diode and induc- tor is equal to the short-circuit current limit of the switch (typically 4.7a for the LT3434). minimum switch on time limitations would prevent the switcher from attaining a sufficiently low duty cycle if switching frequency were maintained at 200khz, so frequency is reduced by about 4:1 when the fb pin voltage drops below 0.4v (see frequency foldback graph). in addition, if the current in the switch exceeds 1.5 times the current limitations speci- fied by the v c pin, due to minimum switch on time, the LT3434 will skip the next switch cycle. as the feedback voltage rises, the switching frequency increases to 200khz with 0.95v on the fb pin. during frequency foldback, external syncronization is disabled to prevent interference with foldback operation. frequency foldback does not affect operation during normal load conditions. in addition to lowering switching frequency the soft-start ramp rate is also affected by the feedback voltage. large capacitive loads or high input voltages can cause a high input current surge during start-up. the soft-start func- tion reduces input current surge by regulating switch current via the v c pin to maintain a constant voltage ramp rate (dv/dt) at the output. a capacitor (c1 in figure 2) from the c ss pin to the output determines the maximum output dv/dt. when the feedback voltage is below 0.4v, the v c pin will rise, resulting in an increase in switch current and output voltage. if the dv/dt of the output causes the current through the c ss capacitor to exceed i css the v c voltage is reduced resulting in a constant dv/dt at the output. as the feedback voltage increases i css increases, resulting in an increased dv/dt until the soft-start function is defeated with 0.9v present at the fb pin. the soft-start function does not affect operation during normal load conditions. however, if a momentary short (brown out condition) is present at the output which causes the fb voltage to drop below 0.9v, the soft-start circuitry will become active. input capacitor step-down regulators draw current from the input supply in pulses. the rise and fall times of these pulses are very fast. the input capacitor is required to reduce the voltage ripple this causes at the input of LT3434 and force the switching current into a tight local loop, thereby minimiz- ing emi. the rms ripple current can be calculated from: i i v vvv ripple rms out in out in out () C = () ceramic capacitors are ideal for input bypassing. at 200khz switching frequency input capacitor values in the range of 4.7 f to 20 f are suitable for most applications. if opera- tion is required close to the minimum input required by the LT3434 a larger value may be required. this is to prevent excessive ripple causing dips below the minimum operat- ing voltage resulting in erratic operation. input voltage transients caused by input voltage steps or by hot plugging the LT3434 to a pre-powered source such as a wall adapter can exceed maximum v in ratings. the sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic inductance of the leads. this energy will cause the input voltage to swing above the dc level of input power source and it may exceed the maximum voltage rating of the input capacitor and LT3434. all input voltage transient sequences should be observed at the v in pin of the LT3434 to ensure that absolute maximum voltage ratings are not violated. the easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low esr input capacitor. the selected capacitor needs to have the right amount of esr to critically damp the resonant circuit formed by the input lead inductance and the input capacitor. the typical values of esr will fall in the range of 0.5 ? to 2 ? and capacitance will fall in the range of 5 f to 50 f. if tantalum capacitors are used, values in the 22 f to 470 f range are generally needed to minimize esr and meet ripple current and surge ratings. care should be
LT3434 11 3434f applicatio s i for atio wu uu unlike the input capacitor rms, ripple current in the output capacitor is normally low enough that ripple cur- rent rating is not an issue. the current waveform is triangular with a typical value of 200ma rms . the formula to calculate this is: output capacitor ripple current (rms) i vvv lfv ripple rms out in out in () .C = ()( ) ()()( ) = 029 12 i p-p ceramic capacitors higher value, lower cost ceramic capacitors are now becoming available. they are generally chosen for their good high frequency operation, small size and very low esr (effective series resistance). low esr reduces output ripple voltage but also removes a useful zero in the loop frequency response, common to tantalum capacitors. to compensate for this a resistor r c can be placed in series with the v c compensation capacitor c c (figure 10). care must be taken however since this resistor sets the high frequency gain of the error amplifier including the gain at the switching frequency. if the gain of the error amplifier is high enough at the switching frequency output ripple voltage (although smaller for a ceramic output capacitor) may still affect the proper operation of the regulator. a filter capacitor c f in parallel with the r c /c c network, along with a small feedforward capacitor c fb , is suggested to control possible ripple at the v c pin. the LT3434 can be stabilized using a 100 f ceramic output capacitor and v c component values of c c = 4700pf, r c = 10k, c f = 470pf and c fb = 27pf. output ripple voltage figure 3 shows a typical output ripple voltage waveform for the LT3434. ripple voltage is determined by the impedance of the output capacitor and ripple current through the inductor. peak-to-peak ripple current through the inductor into the output capacitor is: i vvv vlf out in out in p-p = () ()()() C taken to ensure the ripple and surge ratings are not exceeded. the avx tps and kemet t495 series are surge rated avx recommends derating capacitor operating volt- age by 2:1 for high surge applications. output capacitor the output capacitor is normally chosen by its effective series resistance (esr) because this is what determines output ripple voltage. to get low esr takes volume, so physically smaller capacitors have higher esr. the esr range for typical LT3434 applications is 0.05 ? to 0.2 ? . a typical output capacitor is an avx type tps, 100 f at 10v, with a guaranteed esr less than 0.1 ? . this is a d size surface mount solid tantalum capacitor. tps capacitors are specially constructed and tested for low esr, so they give the lowest esr for a given volume. the value in microfarads is not particularly critical and values from 22 f to greater than 500 f work well, but you cannot cheat mother nature on esr. if you find a tiny 22 f solid tantalum capacitor, it will have high esr and output ripple voltage could be unacceptable. table 2 shows some typical solid tantalum surface mount capacitors. table 2. surface mount solid tantalum capacitor esr and ripple current e case size esr max ( ? ) ripple current (a) avx tps 0.1 to 0.3 0.7 to 1.1 d case size avx tps 0.1 to 0.3 0.7 to 1.1 c case size avx tps 0.2 0.5 many engineers have heard that solid tantalum capacitors are prone to failure if they undergo high surge currents. this is historically true and type tps capacitors are specially tested for surge capability but surge ruggedness is not a critical issue with the output capacitor. solid tantalum capacitors fail during very high turn-on surges which do not occur at the output of regulators. high discharge surges, such as when the regulator output is dead shorted, do not harm the capacitors.
LT3434 12 3434f applicatio s i for atio wu uu for high frequency switchers the ripple current slew rate is also relevant and can be calculated from: di dt v l in = peak-to-peak output ripple voltage is the sum of a triwave created by peak-to-peak ripple current times esr and a square wave created by parasitic inductance (esl) and ripple current slew rate. capacitive reactance is assumed to be small compared to esr or esl. v i esr esl di dt ripple = ()( ) + () p-p example: with v in = 12v, v out = 3.3v, l = 33 h, esr = 0.08 ? , esl = 10nh: i p-p = ()( ) () ? ()() = == 33 12 33 12 33 6 200 3 0 362 12 33 5 363 5 .C. . .C . ee a di dt e e v ripple = (0.362a)(0.08) + (10e C 9)(363e3) = 0.0289 + 0.003 = 32mv p-p maximum output load current maximum load current for a buck converter is limited by the maximum switch current rating (i pk ). the minimum peak current rating for the LT3434 is 3a. unlike most current mode converters, the LT3434 maximum switch current limit does not fall off at high duty cycles. most current mode converters suffer a drop off of peak switch current for duty cycles above 50%. this is due to the effects of slope compensation required to prevent subharmonic oscillations in current mode converters. (for detailed analysis, see application note 19.) the LT3434 is able to maintain peak switch current limit over the full duty cycle range by using patented circuitry to cancel the effects of slope compensation on peak switch current without affecting the frequency compensation it provides. maximum load current would be equal to maximum switch current for an infinitely large inductor, but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. the following formula assumes continuous mode operation, implying that the term on the right (i p-p /2) is less than i out . ii vvv lfv i i out max pk out in out in pk p () C C C = ()( ) ()()( ) = 2 -p 2 discontinuous operation occurs when: i vvv lfv out dis out in out in () C ()()( ) () 2 for v out = 5v, v in = 8v and l = 20 h: i ee a out max () C C C C. . = ()( ) ()()() == 3 58 5 2 20 6 200 3 8 3 0 24 2 76 note that there is less load current available at the higher input voltage because inductor ripple current increases. at v in = 15v, duty cycle is 33% and for the same set of conditions: i ee a out max () C C C C. . = ()( ) ()()() == 3 515 5 2 20 6 200 3 15 3 0 42 2 58 figure 3. LT3434 ripple voltage waveform v out 10mv/div 100 f 75m ? tantalum v out 10mv/div 100 f ceramic i sw 10v/div i load = 2a 1 s/div 3434 f03
LT3434 13 3434f applicatio s i for atio wu uu to calculate actual peak switch current in continuous mode with a given set of conditions, use: ii vvv lfv sw pk out out in out in () C =+ () ()()( ) 2 if a small inductor is chosen which results in discontinous mode operation over the entire load range, the maximum load current is equal to: i iflv vvv out max pk in out in out () C = ()( )( ) ()( ) 2 2 2 choosing the inductor for most applications the output inductor will fall in the range of 15 h to 100 h. lower values are chosen to reduce physical size of the inductor. higher values allow more output current because they reduce peak current seen by the LT3434 switch, which has a minimum 3a limit. higher values also reduce output ripple voltage and reduce core loss. when choosing an inductor you might have to consider maximum load current, core and copper losses, allow- able component height, output voltage ripple, emi, fault current in the inductor, saturation and of course cost. the following procedure is suggested as a way of han- dling these somewhat complicated and conflicting requirements. 1. choose a value in microhenries such that the maximum load current plus half of the inductor ripple current is less than the minimum peak switch current (i pk ). choosing a small inductor with lighter loads may result in discontinuous mode of operation, but the LT3434 is designed to work well in either mode. assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. if maxi- mum load current is 1a, for instance, a 1a inductor may not survive a continuous 4a overload condition. for applications with a duty cycle above 50%, the inductor value should be chosen to obtain an inductor ripple current of less than 40% of the peak switch current. 2. calculate peak inductor current at full load current to ensure that the inductor will not saturate. peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so dont omit this step. powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. other core materials fall somewhere in between. the following formula assumes continuous mode of opera- tion, but it errs only slightly on the high side for discon- tinuous mode, so it can be used for all conditions. table 3. inductor selection criteria vendor/ value i dc dcr height part no. ( h) (amps) (ohms) (mm) sumida cdrh104r-150 15 3.6 0.050 4 cdrh104r-220 22 2.9 0.073 4 cdrh104r-330 33 2.3 0.093 4 cdrh124-220 22 2.9 0.066 4.5 cdrh124-330 33 2.7 0.097 4.5 cdrh127-330 33 3.0 0.065 8 cdrh127-470 47 2.5 0.100 8 cei122-220 22 2.3 0.085 3 coiltronics up3b-330 33 3 0.069 6.8 up3b-470 47 2.4 0.108 6.8 up4b-680 68 4.3 0.120 7.9 coilcraft do3316p-153 15 3 0.046 5.2 do5022p-683 68 3.5 0.130 7.1
LT3434 14 3434f applicatio s i for atio wu uu ii vvv flv peak out out in out in =+ () ()( )( ) C 2 v in = maximum input voltage f = switching frequency, 200khz 3. decide if the design can tolerate an open core geom- etry like a rod or barrel, which have high magnetic field radiation, or whether it needs a closed core like a toroid to prevent emi problems. this is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic field radiation will be a problem. 4. after making an initial choice, consider the secondary things like output voltage ripple, second sourcing, etc. use the experts in the linear technologys applications department if you feel uncertain about the final choice. they have experience with a wide range of inductor types and can tell you about the latest developments in low profile, surface mounting, etc. short-circuit considerations the LT3434 is a current mode controller. it uses the v c node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. the internal clamp on the v c node, nominally 2.2v, then acts as an output switch peak current limit. this action becomes the switch current limit specification. the maximum available output power is then determined by the switch current limit. a potential controllability problem could occur under short-circuit conditions. if the power supply output is short circuited, the feedback amplifier responds to the low output voltage by raising the control voltage, v c , to its peak current limit value. ideally, the output switch would be turned on, and then turned off as its current exceeded the value indicated by v c . however, there is finite response time involved in both the current comparator and turn-off of the output switch. these result in a typical minimum on time of 250ns . when combined with the large ratio of v in to (v f + i ? r), the diode forward voltage plus inductor i ? r voltage drop, the potential exists for a loss of control. expressed mathematically the requirement to maintain control is: ft vir v on f in ? ? + where: f = switching frequency t on = switch on time v f = diode forward voltage v in = input voltage i ? r = inductor i ? r voltage drop if this condition is not observed, the current will not be limited at i pk but will cycle-by-cycle ratchet up to some higher value. using the nominal LT3434 clock frequency of 200khz, a v in of 40v and a (v f + i ? r) of say 0.7v, the maximum t on to maintain control would be approximately 90ns, an unacceptably short time. the solution to this dilemma is to slow down the oscillator to allow the current in the inductor to drop to a sufficiently low value such that the current doesnt continue to ratchet higher. when the fb pin voltage is abnormally low thereby indicating some sort of short-circuit condition, the oscil- lator frequency will be reduced. oscillator frequency is reduced by a factor of 4 when the fb pin voltage is below 0.4v and increases linearly to its typical value of 200khz at a fb voltage of 0.95v (see typical performance character- istics). in addition, if the current in the switch exceeds 1.5 ? i pk current demanded by the v c pin, the LT3434 will skip the next on cycle effectively reducing the oscillator fre- quency by a factor of 2. these oscillator frequency reduc- tions during short-circuit conditions allow the LT3434 to maintain current control. soft-start for applications where [v in /(v out + v f )] ratios > 10 or large input surge currents cant be tolerated, the LT3434 soft-start feature should be used to control the output capacitor charge rate during start-up, or during recovery from an output short circuit thereby adding additional control over peak inductor current. the soft-start function
LT3434 15 3434f c css = 1000pf c css = 0.01 f c css = 0.1 f applicatio s i for atio wu uu limits the switch current via the v c pin to maintain a constant voltage ramp rate (dv/dt) at the output capacitor. a capacitor (c1 in figure 2) from the c ss pin to the regulated output voltage determines the output voltage ramp rate. when the current through the c ss capacitor exceeds the c ss threshold (i css ), the voltage ramp of the output capacitor is limited by reducing the v c pin voltage. the c ss threshold is proportional to the fb voltage (see typical performance characteristics) and is defeated for fb voltages greater than 0.9v (typical). the output dv/dt can be approximated by: dv dt i c css ss = but actual values will vary due to start-up load conditions, compensation values and output capacitor selection. average input current is greatly reduced resulting in higher efficiency. the minimum average input current depends on the v in to v out ratio, v c frequency compensation, feedback divider network and schottky diode leakage. it can be approxi- mated by the following equation: iii v v iii in avg vins shdn out in biass fb s () ? ++ ? ? ? ? ? ? ++ () () where i vins = input pin current in sleep mode v out = output voltage v in = input voltage i biass = bias pin current in sleep mode i fb = feedback network current i s = catch diode reverse leakage at v out = low current efficiency (non burst mode operation) example: for v out = 3.3v, v in = 12v iaa aaa aa a a in avg () . .. . =++ ? ? ? ? ? ? + + () () =++= 45 5 33 12 125 12 5 0 5 085 45 5 44 99 burst mode operation to enhance efficiency at light loads, the LT3434 automati- cally switches to burst mode operation which keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode operation, the LT3434 delivers short bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. in addition, v in and bias quiescent currents are reduced to typically 45 a and 125 a respec- tively during the sleep time. as the load current decreases towards a no load condition, the percentage of time that the LT3434 operates in sleep mode increases and the figure 5. i q vs v in input voltage (v) 0 0 supply current ( a) 50 100 10 20 30 40 3434 f05 50 150 25 75 125 60 v out = 3.3v during the sleep portion of the burst mode cycle, the v c pin voltage is held just below the level needed for normal operation to improve transient response. see the typical performance characteristics section for burst and tran- sient response waveforms. figure 4. v out dv/dt v out 1v/div v in = 12v 1ms/div 3434 f04 v out = 3.3v i load = 500ma
LT3434 16 3434f table 4. catch diode selection criteria i q at 125 c efficiency leakage v in =12v v in =12v v out = 3.3v v f at 1a v out = 3.3 v out = 3.3v diode 25 c 125 c25 c 125 ci l = 0a i l = 1a ir 10bq100 0.0 a59 a 0.72v 0.58v 125 a 78.2% diodes inc. 0.1 a 242 a 0.48v 0.41v 215 a 82% b260sma diodes inc. 0.2 a 440 a 0.45v 0.36v 270 a 82.8% b360smb ir 1 a 1.81ma 0.42v 0.34v 821 a 82.7% mbrs360tr ir 30bq100 1.7 a 2.64ma 0.40v 0.32v 1088 a 80.3% applicatio s i for atio wu uu if a no load condition can be anticipated, the supply current can be further reduced by cycling the shdn pin at a rate higher than the natural no load burst frequency. figure 6 shows burst mode operation with the shdn pin. v out burst ripple is maintained while the average supply current drops to 15 a. the pg pin will be active low during the on portion of the shdn waveform due to the c t capaci- tor discharge when shdn is taken low. see the power good section for further information. lack of a significant reverse recovery time. schottky diodes are generally available with reverse voltage ratings of 60v and even 100v and are price competitive with other types. the effect of reverse leakage and forward drop on effi- ciency for various schottky diodes is shown in table 4. as can be seen these are conflicting parameters and the user must weigh the importance of each specification in choos- ing the best diode for the application. the use of so-called ultrafast recovery diodes is gener- ally not recommended. when operating in continuous mode, the reverse recovery time exhibited by ultrafast diodes will result in a slingshot type effect. the power internal switch will ramp up v in current into the diode in an attempt to get it to recover. then, when the diode has finally turned off, some tens of nanoseconds later, the v sw node voltage ramps up at an extremely high dv/dt, per- haps 5v to even 10v/ns! with real world lead inductances the v sw node can easily overshoot the v in rail. this can result in poor rfi behavior and, if the overshoot is severe enough, damage the ic itself. boost pin for most applications the boost components are a 0.68 f capacitor and a mmsd914 diode. the anode is typically connected to the regulated output voltage to generate a voltage approximately v out above v in to drive the output stage (figure 7a). however, the output stage discharges the boost capacitor during the on time of the switch. the output driver requires at least 2.5v of headroom through- out this period to keep the switch fully saturated. if the figure 6. burst mode with shutdown pin v out 50mv/div v shdn 2v/div i sw 500ma/div v in = 12v time (50ms/div) 3434 g16 v out = 3.3v i q = 15 a catch diode the catch diode carries load current during the sw off time. the average diode current is therefore dependent on the switch duty cycle. at high input to output voltage ratios the diode conducts most of the time. as the ratio ap- proaches unity the diode conducts only a small fraction of the time. the most stressful condition for the diode is when the output is short circuited. under this condition the diode must safely handle i peak at maximum duty cycle. to maximize high and low load current efficiency a fast switching diode with low forward drop and low reverse leakage should be used. low reverse leakage is critical to maximize low current efficiency since its value over tem- perature can potentially exceed the magnitude of the LT3434 supply current. low forward drop is critical for high current efficiency since the loss is proportional to forward drop. these requirements result in the use of a schottky type diode. dc switching losses are minimized due to its low forward voltage drop and ac behavior is benign due to its
LT3434 17 3434f applicatio s i for atio wu uu output voltage is less than 3.3v it is recommended that an alternate boost supply is used. the boost diode can be connected to the input (figure 7b) but care must be taken to prevent the boost voltage (v boost = v in ? 2) from exceeding the boost pin absolute maximum rating. the additional voltage across the switch driver also increases power loss and reduces efficiency. if available, an inde- pendent supply can be used to generate the required boost voltage (figure 7c). tying boost to v in or an independent supply may reduce efficiency but it will re- duce the minimum v in required to start-up with light loads. if the generated boost voltage dissipates too much power at maximum load, the boost voltage the LT3434 sees can be reduced by placing a zener diode in series with the boost diode (figure 7a option). a 0.68 f boost capacitor is recommended for most appli- cations. almost any type of film or ceramic capacitor is suitable but the esr should be <1 ? to ensure it can be fully recharged during the off time of the switch. the capacitor value is derived from worst-case conditions of 4700ns on time, 65ma boost current and 0.7v discharge ripple. the boost capacitor value could be reduced under less de- manding conditions but this will not improve circuit opera- tion or efficiency. under low input voltage and low load conditions a higher value capacitor will reduce discharge ripple and improve start-up operation. shutdown function and undervoltage lockout the shdn pin on the LT3434 controls the operation of the ic. when the voltage on the shdn pin is below the 1.2v shutdown threshold the LT3434 is placed in a zero supply current state. driving the shdn pin above the shutdown threshold enables normal operation. the shdn pin has an internal sink current of 3 a. in addition to the shutdown feature, the LT3434 has an undervoltage lockout function. when the input voltage is below 2.4v, switching will be disabled. the undervoltage lockout threshold doesnt have any hysteresis and is mainly used to insure that all internal voltages are at the correct level before switching is enabled. if an undervolt- age lockout function with hysteresis is needed to limit input current at low v in to v out ratios refer to figure 8 and the following: vr v r v r iv v vr r uvlo shdn shdn shdn shdn hyst out =++ ? ? ? ? ? ? + = () 1 32 1 3 r1 should be chosen to minimize quiescent current during normal operation by the following equation: r vv i in shdn max 1 2 15 = () () C . () boost LT3434 v boost C v sw = v out v boost(max) = v in + v out v in v out optional (7a) v in sw gnd boost LT3434 v boost C v sw = v dc v boost(max) = v dc + v in v in v dc d ss 3434 f07 v out (7c) v in sw gnd boost LT3434 v boost C v sw = v in v boost(max) = 2v in v in v out (7b) v in sw gnd figure 7. boost pin configurations
LT3434 18 3434f applicatio s i for atio wu uu example: r a m r m m a m k 1 12 2 155 13 3 513 1 65 1 13 649 408 = () = ? = ? () = ?? ? ? = C . . . . CC . . (nearest 1% 6.49m ) r2 = 1.3 7 C 1.3 1.3m (nearest 1% 412k) see the typical performance characteristics section for graphs of shdn and v in currents verses input voltage. synchronizing oscillator synchronization to an external input is achieved by connecting a ttl logic-compatible square wave with a duty cycle between 30% and 70% to the LT3434 sync pin. the synchronizing range is equal to initial operating frequency up to 700khz. this means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency (230khz), not the typical oper- ating frequency of 200khz. caution should be used when synchronizing above 230khz because at higher sync frequencies the amplitude of the internal slope compen- sation used to prevent subharmonic switching is re- duced. this type of subharmonic switching only occurs at input voltages less than twice output voltage. higher inductor values will tend to eliminate this problem. see figure 8. undervoltage lockout enable 1.3v 3434 f08 3 a shdn r2 2.4v C + shdn comp C + v in comp 15 v in v out LT3434 4 r1 r3 frequency compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensa- tion. application note 19 has more details on the theory of slope compensation. if the fb pin voltage is below 0.9v (power-up or output short-circuit conditions) the sync function is disabled. this allows the frequency foldback to operate to avoid and hazardous conditions for the sw pin. if no synchronization is required this pin should be con- nected to ground. power good the LT3434 contains a power good block which consists of a comparator, delay timer and active low flag that allows the user to generate a delayed signal after the power good threshold is exceeded. referring to figure 2, the pgfb pin is the positive input to a comparator whose negative input is set at v pgfb . when pgfb is taken above v pgfb , current (i css ) is sourced into the c t pin starting the delay period. when the voltage on the pgfb pin drops below v pgfb the c t pin is rapidly discharged resetting the delay period. the pgfb voltage is typically generated by a resistive divider from the regu- lated output or input supply. the capacitor on the c t pin determines the amount of delay time between the pgfb pin exceeding its threshold (v pgfb ) and the pg pin set to a high impedance state. when the pgfb pin rises above v pgfb current is sourced (i ct ) from the c t pin into the external capacitor. when the voltage on the external capacitor reaches an internal clamp (v ct ), the pg pin becomes a high impedance node. the resultant pg delay time is given by t = c ct ?(v ct )/(i ct ). if the voltage on the pgfb pin drops below its v pgfb , c ct will be discharged rapidly and pg will be active low with a 200 a sink capability. if the shdn pin is taken below its threshold during normal operation, the c t pin will be discharged and pg inactive, resulting in a non power good cycle when shdn is taken above its threshold. figure 9 shows the power good operation with pgfb connected to fb and the capacitance on c t = 0.1 f. figure 10 shows several different configurations for the LT3434 power good circuitry.
LT3434 19 3434f applicatio s i for atio wu uu figure 9. power good v out 500mv/div pg 100k to v in v ct 500mv/div v shdn 2v/div time (10ms/div) 3434 f09 v in pg pgfb LT3434 pg at 80% v out with 100ms delay 0.27 f c out c out 200k v out = 3.3v 153k 12k 100k fb c t v in pg pgfb LT3434 v out disconnect at 80% v out with 100ms delay 0.27 f 200k v out = 3.3v 153k 12k 100k fb c t v in pg pgfb LT3434 pg at v in > 4v with 100ms delay 0.27 f v out = 3.3v 200k 511k 200k 100k 165k fb c t v in pg pgfb LT3434 v out disconnect 3.3v logic signal with 100 s delay 270pf 200k v out = 12v 3434 f10 866k 100k fb c t c out c out figure 10. power good circuits layout considerations as with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. for maximum efficiency switch rise and fall times are typically in the nanosecond range. to prevent noise both radiated and conducted the high speed switching current path, shown in figure 11, must be kept as short as possible. this is implemented in the suggested layout of figure 12. short- ening this path will also reduce the parasitic trace induc- tance of approximately 25nh/inch. at switch off, this
LT3434 20 3434f applicatio s i for atio wu uu parasitic inductance produces a flyback spike across the LT3434 switch. when operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the LT3434 that may exceed its absolute maximum rating. a ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. the v c and fb components should be kept as far away as possible from the switch and boost nodes. the LT3434 pinout has been designed to aid in this. the ground for these components should be separated from the switch current path. failure to do so will result in poor stability or subharmonic like oscillation. board layout also has a significant effect on thermal resistance. pin 8 and the exposed die pad, pin 17, are a continuous copper plate that runs under the LT3434 die. this is the best thermal path for heat out of the package. reducing the thermal resistance from pin 8 and exposed pad onto the board will reduce die temperature and in- crease the power capability of the LT3434. this is achieved by providing as much copper area as possible around the exposed pad. adding multiple solder filled feedthroughs under and around this pad to an internal ground plane will also help. similar treatment to the catch diode and coil terminations will reduce any additional heating effects. thermal calculations power dissipation in the LT3434 chip comes from four sources: switch dc loss, switch ac loss, boost circuit current, and input quiescent current. the following formu- las show how to calculate each of these losses. these formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. switch loss: p ri v v tivf sw sw out out in eff out in = ()( ) + ()( )()() 2 12 / boost current loss: p vi v boost out out in = () () 2 36 / quiescent current loss: p q = v in (0.0015) + v out (0.001) r sw = switch resistance ( 0.15 when hot ) t eff = effective switch current/voltage overlap time (t r + t f + t ir + t if ) t r = (v in /1.2)ns t f = (v in /1.7)ns t ir = t if = (i out /0.2)ns f = switch frequency figure 12. suggested layout figure 11. high speed switching path nc r2 c2 c5 r1 r3 c4 sw v in v in sw boost tcap gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pgood shdn sync pgfb fb v c bias c ss 3434 f12 c3 gnd gnd d1 l1 v out c1 c2 d2 minimize d1-c3 loop v in kelvin sense feedback trace and keep separate from bias trace connect pin 8 gnd to the pin 17 exposed pad gnd place via's under exposed pad to a bottom plane to enhance thermal conductivity LT3434 c2 c1 3434 f11 d1 l1 v in LT3434 v out v in sw 42 high frequency circulation path + load
LT3434 21 3434f applicatio s i for atio wu uu example: with v in = 40v, v out = 5v and i out = 2a: pee p p sw boost q = ( )()() + () () ()( )( ) += = () () = = () + () = 015 2 5 40 77 9 12 2 40 200 3 008 062 07 5240 40 003 40 0 0015 5 0 001 0 07 2 2 . C/ ... / . ... total power dissipation is: p tot = 0.7 + 0.03 + 0.07 = 0.8 thermal resistance for the LT3434 package is influenced by the presence of internal or backside planes. with a full plane under the fe16 package, thermal resistance will be about 45 c/w. no plane will increase resistance to about 150 c/w. to calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: t j = t a + q ja (p tot ) with the fe16 package (q ja = 45 c/w) at an ambient temperature of 70 c: t j = 70 + 45(0.8) = 106 c input voltage vs operating frequency considerations the absolute maximum input supply voltage for the LT3434 is specified at 60v. this is based solely on internal semi- conductor junction breakdown effects. due to internal power dissipation the actual maximum v in achievable in a particular application may be less than this. a detailed theoretical basis for estimating internal power loss is given in the section thermal considerations. note that ac switching loss is proportional to both operating frequency and output current. the majority of ac switch- ing loss is also proportional to the square of input voltage. for example, while the combination of v in = 40v, v out = 5v at 2a and f osc = 200khz may be easily achievable, simultaneously raising v in to 60v and f osc to 700khz is not possible. nevertheless, input voltage transients up to 60v can usually be accommodated, assuming the result- ing increase in internal dissipation is of insufficient time duration to raise die temperature significantly. a second consideration is controllability. a potential limi- tation occurs with a high step-down ratio of v in to v out , as this requires a correspondingly narrow minimum switch on time. an approximate expression for this (assuming continuous mode operation) is given as follows: t on(min) = v out + v f /v in (f osc ) where: v in = input voltage v out = output voltage v f = schottky diode forward drop f osc = switching frequency a potential controllability problem arises if the LT3434 is called upon to produce an on time shorter than its typical value of 250ns. feedback loop action will lower then reduce the v c control voltage to the point where some sort of cycle-skipping or burst mode behavior is exhibited. in summary: 1. be aware that the simultaneous requirements of high v in , high i out and high f osc may not be achievable in practice due to internal dissipation. the thermal con- siderations section offers a basis to estimate internal power. in questionable cases a prototype supply should be built and exercised to verify acceptable operation. 2. the simultaneous requirements of high v in , low v out and high f osc can result in an unacceptably short minimum switch on time. cycle skipping and/or burst mode behavior will result although correct output volt- age is usually maintained. frequency compensation before starting on the theoretical analysis of frequency response the following should be rememberedthe worse the board layout, the more difficult the circuit will be to stabilize. this is true of almost all high frequency analog circuits. read the layout considerations section first. common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/or
LT3434 22 3434f applicatio s i for atio wu uu figure 14. overall loop response figure 13. model for loop response catch diode and connecting the v c compensation to a ground track carrying significant switch current. in addi- tion the theoretical analysis considers only first order non- ideal component behavior. for these reasons, it is important that a final stability check is made with production layout and components. the LT3434 uses current mode control. this alleviates many of the phase shift problems associated with the inductor. the basic regulator loop is shown in figure 12. the LT3434 can be considered as two g m blocks, the error amplifier and the power stage. figure 13 shows the overall loop response with a 470pf v c capacitor and a typical 100 f tantalum output capacitor. the response is set by the following terms: error amplifier: dc gain is set by g m and r o : ea gain = 650 ? 1.5m = 975 ? the pole set by c f and r l : ea pole = 1/(2 ? 1.5m ? 470pf) = 226hz unity gain frequency is set by c f and g m : ea unity gain frequency = 650 f/(2 ? 470pf) = 220khz powerstage: dc gain is set by g m and r l (assume 10 ? ): ps dc gain = 6 ? 10 = 60 pole set by c out and r l : ps pole = 1/(2 ? 100 f ? 10) = 159hz unity gain set by c out and g m : ps unity gain freq = 6/(2 ? 100 f) = 94khz. tantalum output capacitor zero is set by c out and c out esr output capacitor zero = 1/(2 ? 100 f ? 0.1) = 15.9khz the zero produced by the esr of the tantalum output capacitor is very useful in maintaining stability. if the esr of the output capacitor is low or better transient response is required, a zero can be added to the loop using a resistor (r c ) in series with the compensation capacitor (c c ). as the value of r c is increased, transient response will C + current mode power stage g m = 6 ? g m = 650 ? 1.25v v c LT3434 error amp 1.5m r c r1 fb 12 11 sw sw 2 5 esr output r2 c out 3434 f13 c fb c f c c frequency (hz) 0 phase (deg) 120 80 40 160 180 C80 gain (db) 0 40 C40 80 100 100 1k 10k 100k 3434 f14 1m 10 v out = 3.3v c out = 100 f, 0.1 ? c f = 470pf r c = 10k c c = 4700pf i load = 1a generally improve but two effects limit its value. first, the combination of output capacitor esr and a large r c may stop loop gain rolling off altogether. second, if the loop gain is not rolled off sufficiently at the switching frequency output ripple will perturb the v c pin enough to cause unstable duty cycle switching similar to subharmonic oscillation. this may not be apparent at the output. small- signal analysis will not show this since a continuous time system is assumed. when checking loop stability the circuit should be oper- ated over the applications full voltage, current and tem- perature range. any transient loads should be applied and the output voltage monitored for a well-damped behavior.
LT3434 23 3434f package descriptio u fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc fe16 (bc) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3434 24 3434f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt/tp 1104 1k printed in usa related parts part number description comments lt1074/lt1074hv 4.4a (i out ), 100khz, high efficiency step-down dc/dc converters v in : 7.3v to 45v/64v, v out(min) : 2.21v, i q : 8.5ma, i sd : 10 a, dd5/7, to220-5/7 lt1076/lt1076hv 1.6a (i out ), 100khz, high efficiency step-down dc/dc converters v in : 7.3v to 45v/64v, v out(min) : 2.21v, i q : 8.5ma, i sd : 10 a, dd5/7, to220-5/7 lt1676 60v, 440ma (i out ), 100khz, high efficiency step-down dc/dc v in : 7.4v to 60v, v out(min) : 1.24v, i q : 3.2ma, i sd : 2.5 a, converter s8 lt1765 25v, 2.75a (i out ), 1.25mhz, high efficiency step-down dc/dc v in : 3v to 25v, v out(min) : 1.20v, i q : 1ma, i sd : 15 a, converter so-8, tssop16e lt1766 60v, 1.2a (i out ), 200khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) : 1.20v, i q : 2.5ma, i sd : 25 a, converter tssop16/e lt1767 25v, 1.2a (i out ), 1.25mhz, high efficiency step-down dc/dc v in : 3v to 25v, v out(min) : 1.20v, i q : 1ma, i sd : 6 a, converter ms8/e lt1776 40v, 550ma (i out ), 200khz, high efficiency step-down dc/dc v in : 7.4v to 40v, v out(min) : 1.24v, i q : 3.2ma, i sd : 30 a, converter n8, s8 ltc ? 1875 1.5a (i out ), 550khz, synchronous step-down dc/dc converter v in : 2.7v to 6v, v out(min) : 0.8v, i q : 15 a, i sd : <1 a, tssop16 lt1940 dual 1.2a (i out ), 1.1mhz, high efficiency step-down dc/dc v in : 3v to 25v, v out(min) : 1.2v, i q : 3.8ma, ms10 converter lt1956 60v, 1.2a (i out ), 500khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) : 1.20v, i q : 2.5ma, i sd : 25 a, converter tssop16/e lt1976 60v, 1.5a (i out ), 200khz, step-down dc/dc v in : 3v to 60v, v out(min) : 1.25v, i q : 100 a, i sd : 4 a, converter tssop16e lt3010 80v, 50ma, low noise linear regulator v in : 1.5v to 80v, v out(min) : 1.28v, i q : 30 a, i sd : <1 a, ms8e ltc3407 dual 600ma (i out ), 1.5mhz, high efficiency step-down dc/dc v in : 2.5v to 5.5v, v out(min) : 0.6v, i q : 40 a ms10 converter ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter v in : 2.5v to 5.5v, v out(min) : 0.8v, i q : 60 a, i sd : <1 a, tssop16e ltc3414 4a (i out ), 4mhz, synchronous step-down dc/dc converter v in : 2.25v to 5.5v, v out(min) : 0.8v, i q : 64 a, i sd : <1 a, tssop20e lt3430 60v, 2.5a (i out ), 200khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) : 1.20v, i q : 2.5ma, i sd : 30 a, converter tssop16e lt3431 60v, 2.5a (i out ), 500khz, high efficiency step-down dc/dc v in : 5.5v to 60v, v out(min) : 1.20v, i q : 2.5ma, i sd : 30 a, converter tssop16e lt3433 60v, 400ma (i out ), 200khz, buck-boost dc/dc converter v in : 5v to 60v, v out : 3.3v to 20v, i q : 100 a, tssop-16e ltc3727/ltc3727-1 36v, 500khz, high efficiency step-down dc/dc controllers v in : 4v to 36v, v out(min) : 0.8v, i q : 670 a, i sd : 20 a, qfn-32, ssop-28

▲Up To Search▲

Price & Availability of LT3434

	To Download LT3434 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .